Efficient Hardware Implementation of SHA-3 Candidate Grøstl using FPGA

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Grøstl - a SHA-3 candidate

Grøstl is a SHA-3 candidate proposal. Grøstl is an iterated hash function with a compression function built from two fixed, large, distinct permutations. The design of Grøstl is transparent and based on principles very different from those used in the SHA-family. The two permutations are constructed using the wide trail design strategy, which makes it possible to give strong statements about th...

متن کامل

Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2

The Hash function has been studied by designers with the goal to improve its performances in terms of area, frequency and throughput. The Hash function is used in many embedded systems to provide security. It is become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and SHA-512 functions. Moreover, the proposed design ha...

متن کامل

A Compact FPGA Implementation of the SHA-3 Candidate ECHO

We propose a compact architecture of the SHA-3 candidate ECHO for the Virtex-5 FPGA family. Our architecture is built around a 8-bit datapath. We show that a careful organization of the chaining variable and the message block in the register file allows one to design a compact control unit based on a 4-bit counter, an 8-bit counter, and a simple Finite State Machine. A fully autonomous implemen...

متن کامل

A Compact Hardware Implementation of SHA-3 Candidate Luffa

In this document, the hardware performances of Luffa-256 are reported. Our implementations mainly target size optimized implementations in ASIC and the smallest architecture can be implemented with only 10.3 KGE while it achieves about 500 Mbps.

متن کامل

Hardware Implementation of the SHA-3 Candidate Skein

Skein is a submission to the NIST SHA-3 hash function competition which has been optimized towards implementation in modern 64-bit processor architectures. This paper investigates the performance characteristics of a high-speed hardware implementation of Skein with a 0.18 μm standard-cell library and on different modern FPGAs. The results allow a first comparison of the hardware performance fig...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: International Journal of Computer Applications

سال: 2012

ISSN: 0975-8887

DOI: 10.5120/8829-2963